The invention relates to simulation environments and in particular to simulating an instruction unit in a random simulation environment to verify address generation interlock (AGI) and AGI early resolution functions.
AGI can occur when an instruction attempts to compute an address by which to reference storage. This address computation (also referred to as “address add”) is typically the addition of some of the following: the contents of one or more registers, a constant value from the instruction, and the address of the branch instruction itself. If a register is used for address generation and that register is modified by a previous instruction (a dependency), then address computation cannot proceed until that register is available. The delay caused by waiting for the register value is known as AGI. AGI occurs in the instruction unit when an instruction which has previously been decoded, but has not yet executed, alters a register which an instruction currently being decoded requires for reference to its upcoming address generation. In certain instructions, the target register future contents are available to the instruction unit prior to execution. To reduce AGI latency, which may lead to improved performance, the instruction unit uses the known register future contents, when available, instead of waiting for the execution unit to update the register of interest. This is referred to as AGI early resolution.
One of the difficulties in verifying the instruction unit for advanced processor design for computers in a random simulation environment has to do with providing random updates to registers in the processor. Currently, it is not possible to provide random updates to the registers for the normal resolution of the AGI functions for the decoding instructions and also to provide early calculated register contents which are stored in the instruction unit for special instructions (known as AGI early resolution).